Method and apparatus to reduce latency and improve throughput of input/output data in a processor
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United States of America Patent
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Jan 20, 2009
Grant Date -
Dec 14, 2006
app pub date -
Jun 8, 2005
filing date -
Jun 8, 2005
priority date (Note) -
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Abstract
Some embodiments include apparatus and method having a register circuit to receive a first portion of a packet from an input/output device, cache memory circuit to receive a second portion of the package, and a processing unit to process at least one of the first and second portions of the packet based on instructions in the processing unit. The processing unit and the register circuit reside on a processor. The first portion of the packet is placed into the register circuit of the processor, bypassing a memory device coupled to the processor. The second portion of the packet is placed into the cache memory circuit of the processor, bypassing the memory device.
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