Negative edge flip-flops for muxscan and edge clock compatible LSSD
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United States of America Patent
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Jan 27, 2009
Grant Date -
Sep 20, 2007
app pub date -
Mar 14, 2006
filing date -
Mar 14, 2006
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method of synchronous digital operation and scan based testing of an integrated circuit using a flip-flop. The flip-flop including a master latch having an input and a clock pin; a slave latch having an output, a first clock pin and a second clock pin, the slave latch connected to the master latch; a first AND gate having a first input, an inverted second input and an output, the output of the first AND gate connected to the first clock pin of the master latch; a second AND gate having a first input, an inverted second input and an output, the output of the second AND gate connected to the second input of the first AND gate and to the first clock pin of the slave latch.
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