Method of forming a stacked semiconductor package
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United States of America Patent
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Feb 3, 2009
Grant Date -
Apr 6, 2006
app pub date -
Nov 22, 2005
filing date -
Mar 9, 2001
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Abstract
Disclosed is a stacking structure of semiconductor chips and semiconductor package using it, capable of achieving an electric insulation even if a conductive wire makes contact with a lower surface of an upper semiconductor chip, while reducing a total thickness thereof and preventing damage. The stacking structure has a substrate formed with a plurality of circuit patterns; a first semiconductor chip bonded to an upper surface of the substrate and having a first plane and a second plane formed with a plurality of input/output pads; a spacer bonded to the second plane of the first semiconductor chip; a second semiconductor chip having first and second planes, the second plane being formed with a plurality of input/output pads, the first plane being provided with an insulating member so as to allow the second semiconductor chip to be bonded to the spacer, a first conductive wire for connecting the input/output pads of the first semiconductor chip to the circuit patterns of the substrate; and a second conductive wire for connecting the input/output pads of the second semiconductor chip to the circuit patterns of the substrate.
First Claim
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- AMKOR TECHNOLOGY, INC.
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Min, Byoung Youl | Seoul , KR | 18 | 339 |
Oh, Kwang Seok | Seoul , KR | 21 | 249 |
Park, Jong Wook | Seoul , KR | 23 | 330 |
Park, Young Kuk | Seoul , KR | 8 | 206 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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