NAND flash memory devices having shielding lines between wordlines and selection lines
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United States of America Patent
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Feb 3, 2009
Grant Date -
Dec 14, 2006
app pub date -
May 11, 2006
filing date -
May 11, 2005
priority date (Note) -
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Abstract
A NAND flash memory having a cell string structure includes a wordline configured to transfer a wordline voltage to a memory cell. A selection line is configured to transfer a selection voltage to a selection transistor connected to the memory cell and at least one shielding line is interposed between the wordline and the selection line and is operable to reduce capacitance-coupling between the wordline and the selection line during a programming operation.
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