Power and ground ring snake pattern to prevent delamination between the gold plated ring and mold resin for wirebond PBGA
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United States of America Patent
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Feb 10, 2009
Grant Date -
N/A
app pub date -
Apr 15, 2008
filing date -
Apr 15, 2008
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An exemplary ball grid array package for a semiconductor device includes an integrated circuit on a substrate, and a first bus on the substrate, the first bus including first portions that extend substantially parallel to the integrated circuit, interleaved with second portions that extend substantially toward the integrated circuit, each second portion having an end contiguous with a first portion and another end contiguous with a another first portion. A first set of wires connects the first bus with a first plurality of nodes on the integrated circuit. The package also includes a second bus and a second set of wires.
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