Semiconductor memory device capable of controlling clock cycle time for reduced power consumption
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United States of America Patent
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Feb 10, 2009
Grant Date -
Nov 9, 2006
app pub date -
Jul 19, 2006
filing date -
May 16, 2002
priority date (Note) -
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Abstract
Some embodiments of the invention include a delay locked loop having a delay line for delaying an input signal. The input signal is generated from a first signal. A delay controller controls the delay line to adjust the timing relationship between the first signal and an internal signal. The delay locked loop also includes cycle control circuitry for controlling the cycle time of the signal entering the delay line and the cycle time of the signal exiting the delay line.
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