Integrated circuit analysis system and method using model checking
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United States of America Patent
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Feb 17, 2009
Grant Date -
Jul 19, 2007
app pub date -
Dec 7, 2005
filing date -
Dec 7, 2005
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Abstract
A method and system for verifying an integrated circuit using a Model Checker at post-silicon time to improve post-silicon assertion-based verification. A dialog is established between the Model Checker and a fabricated integrated circuit under test (ICUT), to increase the state space which is explored. ICUT-based traces from the integrated current are generated, in part based on initial states and assertions provided by the Model Checker or by a user. The Model Checker verifies the integrated circuit by generating Model Checker-based traces from basic logic, which are reproductions of the ICUT-based traces.
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