States encoding in multi-bit flash cells for optimizing error rate
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Feb 17, 2009
Grant Date -
May 11, 2006
app pub date -
Mar 14, 2005
filing date -
Nov 8, 2004
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
To store N bits of M≧2 logical pages, the bits are interleaved and the interleaved bits are programmed to ┌N/M┐ memory cells, M bits per cell. Preferably, the interleaving puts the same number of bits from each logical page into each bit-page of the ┌N/M┐ cells. When the bits are read from the cells, the bits are de-interleaved. The interleaving may be deterministic or random, and may be effected by software or by dedicated hardware.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully