Flash devices with shared word lines
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United States of America Patent
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Feb 24, 2009
Grant Date -
Jun 21, 2007
app pub date -
Dec 21, 2005
filing date -
Dec 21, 2005
priority date (Note) -
In Force
status (Latency Note)
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Abstract
Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.
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