Integrated circuit memory device having delayed write timing based on read response time
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United States of America Patent
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Feb 24, 2009
Grant Date -
Apr 17, 2008
app pub date -
Dec 10, 2007
filing date -
Oct 10, 1997
priority date (Note) -
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Abstract
An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.
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