Methods of providing a family of related integrated circuits of different sizes
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United States of America Patent
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Mar 3, 2009
Grant Date -
N/A
app pub date -
Jan 17, 2006
filing date -
Nov 1, 2005
priority date (Note) -
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Abstract
Methods of manufacturing a family of packaged integrated circuits (ICs) having at least two different logic capacities. A first IC die includes two different portions, of which at least one portion can be deliberately rendered non-operational in some manner (e.g., non-functional, inaccessible, and/or non-programmable) within the package. A first set of the first IC dies are packaged such that both portions of the dies are operational. A second set of the first IC dies are packaged such that only the first portion of each die is operational. Once the first and second sets are packaged and the second set of ICs has been evaluated, a decision is made whether or not to manufacture a second IC die that includes the first portion of the first die, while excluding the second portion.
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