Mechanism for enabling full data bus utilization without increasing data granularity
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United States of America Patent
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Mar 3, 2009
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N/A
app pub date -
Apr 17, 2001
filing date -
Apr 17, 2001
priority date (Note) -
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Abstract
A memory is disclosed comprising a first memory portion, a second memory portion, and an interface, wherein the memory portions are electrically isolated from each other and the interface is capable of receiving a row command and a column command in the time it takes to cycle the memory once. By interleaving access requests (comprising row commands and column commands) to the different portions of the memory, and by properly timing these access requests, it is possible to achieve full data bus utilization in the memory without increasing data granularity.
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