Method for non-volatile memory with background data latch caching during program operations
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United States of America Patent
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Mar 10, 2009
Grant Date -
Oct 19, 2006
app pub date -
May 5, 2006
filing date -
Apr 1, 2005
priority date (Note) -
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Abstract
Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a write operation. In the exemplary embodiment, when the multiple phases of a write operation vary as to the number of states to track, a phase-dependent coding enables efficient utilization of the available data latches, thereby allowing a maximum of surplus latches for background cache operations.
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