Method of manufacturing thin film semiconductor device

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United States of America Patent

PATENT NO 7504327
SERIAL NO

11148426

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Abstract

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In the invention, a low concentration impurity region is formed between a channel formation region and a source region or a drain region in a semiconductor layer and covered with a gate electrode layer in a thin film transistor The semiconductor layer is doped obliquely to the surface thereof using the gate electrode layer as a mask to form the low concentration impurity region. The semiconductor layer is formed to have an impurity region including an impurity element for imparting one conductivity which is different from conductivity of the thin film transistor, thereby being able to minutely control the properties of the thin film transistor.

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Patent Owner(s)

Patent OwnerAddress
SEMICONDUCTOR ENERGY LABORATORY CO LTD398 HASE ATSUGI-SHI KANAGAWA 2430036 ?2430036

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Godo, Hiromichi Kanagawa, JP 174 4071
Isobe, Atsuo Kanagawa , JP 213 5332
Yamaguchi, Tetsuji Kanagawa, JP 216 2209
Yamazaki, Shunpei Tokyo , JP 7534 239327

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