Configurable integrated circuit with parallel non-neighboring offset connections
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United States of America Patent
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Mar 17, 2009
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N/A
app pub date -
Mar 8, 2006
filing date -
Mar 8, 2006
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Abstract
Some aspects of the present invention involve connections in a configurable IC. Some embodiments provide a configurable integrated circuit with a first array of tiles. The first array of tiles has columns and rows of tiles. The IC has a first tile within the first array of tiles. The first tile has a set of outputs. The IC has a second tile in the array of tiles. The second tile has a set of inputs. The IC has a non-neighboring offset connection (NNOC) from an output of the first tile to an input of the second tile. The second tile is offset from the first tile by at least one row and at least two columns or by at least two rows and at least one column.
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