Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages
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United States of America Patent
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Mar 24, 2009
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app pub date -
Jun 22, 2005
filing date -
Jun 22, 2005
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Abstract
A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.
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