Aligning stacked chips using resistance assistance
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United States of America Patent
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Apr 7, 2009
Grant Date -
N/A
app pub date -
Aug 12, 2008
filing date -
Aug 12, 2008
priority date (Note) -
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Abstract
The present invention relates to a method of aligning stacked chips wherein the apparatus and method utilize bumps in the form of exposed metal lines on a first chip. The present invention further relates to taking a resistance measurement to determine a quality of alignment wherein the resistance measurement indicates a direction in which the first chip and the second chip are misaligned.
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