Current compliant sensing architecture for multilevel phase change memory
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United States of America Patent
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Apr 7, 2009
Grant Date -
Jul 10, 2008
app pub date -
Jan 5, 2007
filing date -
Jan 5, 2007
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Abstract
A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.
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