Processor for computing a packed sum of absolute differences and packed multiply-add
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United States of America Patent
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Apr 7, 2009
Grant Date -
May 23, 2002
app pub date -
Nov 6, 2001
filing date -
Mar 31, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to one embodiment, a processor includes a decode unit to decode a packed sum of absolute differences (PSAD) instruction having an opcode format to identify a set of packed data operands. The decode unit initiates a sequence of operations on the set of packed data operands in response to decoding the PSAD instruction. An execution unit performs a first operation of the sequence of operations initiated by the decode logic, and a bus provides the execution unit with the set of packed data operands as identified in accordance with the opcode format.
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