Distributed processing architecture with scalable processing layers
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United States of America Patent
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Apr 7, 2009
Grant Date -
Dec 21, 2006
app pub date -
Mar 27, 2006
filing date -
Dec 3, 2001
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The present invention is a system on chip having a scalable, distributed processing architecture and memory capabilities through a plurality of parallel processing layers. In one embodiment, the processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (Pus), specially designed for conducting a defined set of processing tasks, are in communication with program memories and data memories.
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