US Patent No: 7,518,922

Number of patents in Portfolio can not be more than 2000

NAND type flash memory

ALSO PUBLISHED AS: 20070280031
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Abstract

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A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the number of the “1” data and the “0” data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
KABUSHIKI KAISHA TOSHIBATOKYO25291

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Abe, Takumi Yokohama, JP 32 94
Isobe, Katsuaki Yokohama, JP 91 276
Maejima, Hiroshi Chigasaki, JP 252 882
Takeuchi, Ken Tokyo, JP 233 3766

Cited Art Landscape

Patent Info (Count) # Cites Year
 
KABUSHIKI KAISHA TOSHIBA (1)
* 5,570,315 Multi-state EEPROM having write-verify control circuit 713 1994
 
RENESAS TECHNOLOGY CORP. (1)
* 6,999,371 Semiconductor memory device capable of reducing power consumption during reading and standby 6 2004
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
KABUSHIKI KAISHA TOSHIBA (2)
* 7,876,626 Semiconductor memory device and semiconductor memory system 2 2009
8,902,662 Memory system having nonvolatile semiconductor memories with control operation having high-current and low-current periods 0 2011
 
ALTERA CORPORATION (1)
* 7,978,493 Data encoding scheme to reduce sense current 6 2008
 
OCZ STORAGE SOLUTIONS, INC. (1)
* 8,756,464 Flash memory device and flash memory programming method equalizing wear-level 0 2008
* Cited By Examiner

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