US Patent No: 7,518,922
Number of patents in Portfolio can not be more than 2000
NAND type flash memory
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Apr 14, 2009
Issued date -
May 16, 2007
filing date -
11/749,214
serial no -
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Abstract
A NAND type flash memory included with a memory cell array composed of a plurality of electronically rewritable memory cells arranged in a matrix shape, and a data inversion control section which judges whether a polarity of a “1” data or a “0” data is to be inverted based on the number of the “1” data and the “0” data of the data when data is sent to the plurality of memory cells within a simultaneous write data unit and inverts the data and in the case where it is sent to the memory cell array adds an inversion flag bit to the data which shows the inversion of the polarity.
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 5,570,315 Multi-state EEPROM having write-verify control circuit | 622 | 1994 | |
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| 6,999,371 Semiconductor memory device capable of reducing power consumption during reading and standby | 6 | 2004 | |
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