Reconfigurable SIMD vector processing system
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United States of America Patent
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Apr 14, 2009
Grant Date -
May 1, 2008
app pub date -
Oct 26, 2006
filing date -
Oct 26, 2006
priority date (Note) -
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Abstract
A system may include M N-bit×N-bit multipliers to output M 2N-bit products in a redundant format, a compressor to receive the M 2N-bit products and to generate an MN-bit product in a redundant format based on the M 2N-bit products, and an adder block to receive the M 2N-bit products and the MN-bit product, to select one from the M 2N-bit products or the MN-bit product, and to resolve the selected one of the M 2N-bit products or the MN-bit product to a non-redundant format.
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