Wafer level I/O test and repair enabled by I/O layer
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United States of America Patent
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Apr 21, 2009
Grant Date -
Apr 12, 2007
app pub date -
Oct 7, 2005
filing date -
Oct 7, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A 3D chip having at least one I/O layer connected to other 3D chip layers by a vertical bus such that the I/O layer(s) may accommodate protection and off-chip device drive circuits, customization circuits, translation circuits, conversions circuits and/or built-in self-test circuits capable of comprehensive chip or wafer level testing wherein the I/O layers function as a testhead. Substitution of I/O circuits or structures may be performed using E-fuses or the like responsive to such testing.
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