Method and system for reducing soft-writing in a multi-level flash memory

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United States of America Patent

PATENT NO 7522455
SERIAL NO

11144174

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Abstract

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A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.

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Patent Owner(s)

  • ARTEMIS ACQUISITION LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bartoli, Simone Cambiago, IT 47 502
Bedarida, Lorenzo Milan, IT 54 657
Oddone, Giorgio Genoa, IT 24 169
Tassan, Caser Fabio Milan , IT 15 138

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