Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix
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United States of America Patent
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Apr 21, 2009
Grant Date -
May 27, 2004
app pub date -
Oct 10, 2003
filing date -
Oct 11, 2002
priority date (Note) -
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Abstract
A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.
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