Stack package having guard ring which insulates through-via interconnection plug and method for manufacturing the same
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United States of America Patent
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Apr 28, 2009
Grant Date -
Apr 3, 2008
app pub date -
Dec 29, 2006
filing date -
Sep 30, 2006
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.
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