Reducing memory access bandwidth consumption in a hierarchical packet scheduler

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United States of America Patent

PATENT NO 7525962
APP PUB NO 20060153184A1
SERIAL NO

11024318

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Abstract

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Reducing memory access bandwidth consumption in a hierarchical packet scheduler. A hierarchical packet scheduler is maintained, wherein the hierarchical packet scheduler includes one or more levels, each level including one or more schedulers, wherein one or more threads serve each level. Scheduling operations are performed at each scheduler of the hierarchical packet scheduler by reading a portion of scheduler state from external memory.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTEL CORPORATIONSANTA CLARA, CA29065

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kounavis, Michael Hillsboro, US 20 128
Kumar, Alok Santa Clara, US 81 1496
Yavatkar, Raj Portland, US 33 905

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