Importance

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Abstract

A test system includes respective clock domain crossing circuits coupling memory device signals to a memory device being tested. The clock domain crossing circuit includes a ring buffer into which the respective memory device signal is latched responsive to a first clock signal. The particular buffer into which the memory device signal is latched is determined by a write pointer, which is incremented by the first clock signal. The outputs of the buffers are applied to a multiplexer, which is controlled by a read pointer to couple a memory device signal from one of the buffers to the memory device. The read pointer is incremented by a second clock signal having a timing that is adjustable and may be different from the second clock signal used to increment the read pointer in a clock domain crossing circuit for a different memory device signal.

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First Claim