Methods and apparatus for designing and using micro-targets in overlay metrology
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United States of America Patent
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Apr 28, 2009
Grant Date -
May 3, 2007
app pub date -
Jan 10, 2006
filing date -
Oct 31, 2005
priority date (Note) -
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Abstract
Methods and apparatus for fabricating a semiconductor die including several target structures. A first layer is formed that includes one or more line or trench structures that extend in a first direction. A second layer is formed that includes one or more line or trench structures that extend in a second direction that is perpendicular to the first structure, such that a projection of the target structure along the first direction is independent of the second direction and a projection of the target structure along the second direction is independent of the first direction. A target structure and a method for generating a calibration curve are also described.
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