Method for manufacturing a resistor random access memory with reduced active area and reduced contact areas
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United States of America Patent
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May 5, 2009
Grant Date -
Apr 24, 2008
app pub date -
Oct 24, 2006
filing date -
Oct 24, 2006
priority date (Note) -
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Abstract
A method for manufacturing a memory device comprises patterning a dielectric layer and a conductive layer to align near the center of the top surface of a first contact drain plug and near the center of the top surface of a second contact drain plug. A first electrode is formed on the right sidewalls of the patterned dielectric layer and the conductive layer. A sidewall insulating member has a first sidewall surface and a second sidewall surface where the first sidewall surface of the sidewall insulating member is in contact with a sidewall of the first electrode. A second electrode is formed by depositing an electrode layer overlying the top surface of the sidewall insulating member and the second sidewall of the insulating member and isotropically etching the electrode layer to form the second electrode.
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