Method for forming an integrated semiconductor circuit arrangement
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United States of America Patent
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May 12, 2009
Grant Date -
Jan 19, 2006
app pub date -
May 26, 2005
filing date -
May 28, 2004
priority date (Note) -
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Abstract
Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.
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