Variable size cache memory support within an integrated circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 12, 2009
Grant Date -
Jun 28, 2007
app pub date -
Dec 6, 2006
filing date -
Dec 22, 2005
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully