Semiconductor device and method of manufacturing the same
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United States of America Patent
Stats
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May 19, 2009
Grant Date -
Jan 19, 2006
app pub date -
Sep 23, 2005
filing date -
May 29, 2003
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.
First Claim
Family
International Classification(s)
Cited Art Landscape
| Patent Info | (Count) | # Cites | Year |
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| * 6534375 METHOD OF FORMING A CAPACITOR IN A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE USING A METAL SILICON NITRIDE LAYER TO PROTECT AN UNDERLYING METAL SILICIDE LAYER FROM OXIDATION DURING SUBSEQUENT PROCESSING STEPS | 7 | 2001 | |
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| 6207524 Memory cell with a stacked capacitor | 12 | 1998 | |
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| * 4540607 Selective LPCVD tungsten deposition by the silicon reduction method | 41 | 1983 | |
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| * 6800543 Semiconductor device having a low-resistance gate electrode | 12 | 2002 | |
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| * 5837592 Method for stabilizing polysilicon resistors | 36 | 1995 | |
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| 2003/0123,216 Deposition of tungsten for the formation of conformal tungsten silicide | 97 | 2001 | |
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| 5891785 Process for forming self-aligned silicide | 18 | 1997 | |
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| 6340629 Method for forming gate electrodes of semiconductor device using a separated WN layer | 27 | 1999 | |
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| 6277719 Method for fabricating a low resistance Poly-Si/metal gate | 15 | 1999 | |
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| 6133149 Method of improving thermal stability of tungsten silicide | 6 | 1998 | |
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| 2003/0190,424 Process for tungsten silicide atomic layer deposition | 5 | 2001 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
|---|---|---|---|---|
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Nov 19, 2020 |
| Fee | Large entity fee | small entity fee | micro entity fee |
|---|---|---|---|
| Surcharge - 11.5 year - Late payment within 6 months | $160.00 | $80.00 | $40.00 |
| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
| Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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