Tiled construction of layered materials
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United States of America Patent
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May 19, 2009
Grant Date -
May 18, 2006
app pub date -
Oct 12, 2005
filing date -
Oct 12, 2004
priority date (Note) -
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status (Latency Note)
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Abstract
A method is described for combining the diverse strengths of two materials in a tiled film construction. The first material provides a foundation of intersecting grid lines on a substrate and the second material is contained within the grid lines and has a valued property for a particular application. In a preferred embodiment, a tiled dielectric layer has improved low-k dielectric performance while avoiding film stress problems that can lead to delamination or cracking. CTE mismatch is overcome at the cost of an additional masking step. This tiling method and layered binary construction enable Cytop to be used as a high performance low-k dielectric on most substrates including semiconductor wafers and copper panels or foils.
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