Integrated memory controller
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United States of America Patent
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May 19, 2009
Grant Date -
N/A
app pub date -
Oct 23, 2007
filing date -
Jun 14, 2004
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Abstract
A memory system includes Synchronous Dynamic Random Access Memory (SDRAM) A memory controller communicates with the memory, generates an SDRAM clock signal, that receives a bi-directional sampling clock signal (DQS) that is generated based on the SDRAM clock signal, and reads data from the memory based on the DQS.
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