Memory system for a high performance IP processor
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United States of America Patent
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May 19, 2009
Issued Date -
N/A
app pub date -
Jun 10, 2003
filing date -
Jun 11, 2002
priority date (Note) -
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Abstract
A memory system for a high performance IP processor is disclosed. The memory system allows the architecture for an IP processor that may provide capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol layer and may also perform packet inspection through Layer 7. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory. An application running on an initiator or target can in certain instantiations register a region of memory, which is made available to its peer(s) for access directly without substantial host intervention through RDMA data transfer.
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