Attribute cache memory
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United States of America Patent
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May 26, 2009
Grant Date -
Oct 25, 2007
app pub date -
Mar 28, 2006
filing date -
Mar 28, 2006
priority date (Note) -
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Abstract
A memory system according to one embodiment includes a plurality of content addressable word decoders, and memory cells associated with each of the word decoders. A memory system according to another embodiment includes a word decoder storing an identifier which is a subset of a memory address, the word decoder being responsive to a match of the identifier and an incoming subset of the memory address. A memory system according to yet another embodiment includes a word decoder having more than sixteen address line inputs. A memory system according to a further embodiment includes a word decoder array having fewer word decoders than combinations of memory addresses. Methods are also provided.
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