Resistive memory including refresh operation

United States of America Patent

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May 26, 2009
Grant Date
May 22, 2008
app pub date
Nov 22, 2006
filing date
Nov 22, 2006

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Abstract

A memory device includes an array of resistive memory cells, a counter having an increment step based on temperature, and a circuit for refreshing the memory cells in response to the counter exceeding a preset value.

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Patent Owner(s)

Patent Owner	Address
POLARIS INNOVATIONS LIMITED	29 EARLSFORT TERRACE DUBLIN 2 DUBLIN

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G11C:STATIC STORES

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Inventor Name	Address	# of filed Patents	Total Citations
Happ, Thomas	Tarrytown, US	167	4833
Philipp, Jan Boris	Peekskill, US	99	2858

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Resistive memory including refresh operation

Number of patents in Portfolio can not be more than 2000

United States of America Patent

11603636

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PATENT NO	7539050
APP PUB NO	20080117663A1
SERIAL NO	11603636
DOCKET NO

US Family Size	Non-US Coverage
Patent Longevity Expired	Forward Citations

DATE PUBLISHED	PUBLICATION/PATENT NO.	PUBLICATION TYPE
May 26, 2009	US,7539050,B2 US7539050B2	GRANTED PATENT AS SECOND PUBLICATION
May 22, 2008	US,20080117663,A1 US20080117663A1	FIRST PUBLISHED PATENT APPLICATION

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11603636

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