Semiconductor test apparatus and method thereof and multiplexer and method thereof
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United States of America Patent
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May 26, 2009
Grant Date -
May 5, 2005
app pub date -
Oct 29, 2004
filing date -
Oct 31, 2003
priority date (Note) -
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Abstract
A semiconductor test apparatus for determining memory failure, including a first at least one multiplexer. The first at least one multiplexer may include a first transistor and a second transistor, the first transistor and the second transistor being different sizes. The semiconductor may include a scan cell, the scan cell including a second at least one multiplexer. The second at least one multiplexer may include a third transistor and a fourth transistor, the third transistor and the fourth transistor being different sizes. Another semiconductor test apparatus including a plurality of scan cells and a plurality of multiplexers, each of the plurality of scan cells and the plurality of multiplexers formed in a single wrapper.
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