Semiconductor package having dimpled plate interconnections

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7541666
APP PUB NO 20070290336A1
SERIAL NO

11799467

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Abstract

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A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.

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Patent Owner(s)

  • ALPHA & OMEGA SEMICONDUCTOR, LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Liu, Kai Mountain View, US 705 6576
Shi, Lei Shanghai, CN 497 2378
Sun, Ming Sunnyvale, US 234 4469

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