Analog layout module generator and method

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United States of America Patent

PATENT NO 7543262
APP PUB NO 20070130553A1
SERIAL NO

11295268

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Abstract

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In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.

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Patent Owner(s)

Patent OwnerAddress
CADENCE DESIGN SYSTEMS INC2655 SEELY AVENUE BUILDING 5 SAN JOSE CA 95134

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Colwell, Regis R Gibsonia, US 8 150
Fallon, Elias Pittsburgh, US 4 190
Wang, Zhigang Sewickley, US 301 5223

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