Random access of user design states in a configurable IC
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United States of America Patent
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Jun 16, 2009
Grant Date -
Nov 6, 2008
app pub date -
Mar 13, 2006
filing date -
Jul 15, 2005
priority date (Note) -
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Abstract
Some embodiments of the invention is a configurable integrated circuit (IC) that includes (1) several configurable logic circuits, (2) a first routing network for connecting the configurable logic circuits, (3) several user design state (UDS) circuits, and (4) a second network communicatively coupled to the UDS circuits. In least one period during the operation of the IC, the second network receives addresses for a several UDS circuits in a random access manner. In some embodiments, the second network is a debug network for reading randomly state values stored by the addressed UDS circuits during the user-design operation of the IC.
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