Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 16, 2009
Issued Date -
N/A
app pub date -
Aug 13, 2007
filing date -
Oct 8, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully