Semiconductor integrated circuit device and manufacture thereof

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 7550763
APP PUB NO 20070241330A1
SERIAL NO

11808808

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
TESSERA ADVANCED TECHNOLOGIES INC3025 ORCHARD PARKWAY SAN JOSE CA 95134

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kitsukawa, Gorou Kisarazu, JP 6 102
Miyamoto, Toshio Kokubunji, JP 80 1829
Nishimura, Asao Kokubunji, JP 156 3473
Syukuri, Syouji Koganei, JP 6 102

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation