Scalable high performance non-volatile memory cells using multi-mechanism carrier transport
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United States of America Patent
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Jun 30, 2009
Grant Date -
Oct 25, 2007
app pub date -
Jun 25, 2007
filing date -
Feb 25, 2005
priority date (Note) -
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Abstract
A plurality of select gates are formed over a substrate. In one embodiment, the select gates are formed vertically on the sidewalls of trenches. The substrate includes a plurality of diffusion regions that are each formed between a pair of planar select gates. In a vertical embodiment, the diffusion regions are formed at the bottom of the trenches and the tops of the mesas formed by the trenches. An enriched region is formed in the substrate adjacent to and substantially surrounding each diffusion region in the substrate. Each enriched region has a matching conductivity type with the substrate. A gate insulator stack is formed over the substrate and each of the plurality of select gates. A word line is formed over the gate insulator stack.
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