Method of making a wafer level integration package
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United States of America Patent
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Jun 30, 2009
Grant Date -
Dec 25, 2008
app pub date -
Jun 20, 2007
filing date -
Jun 20, 2007
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor package is made by providing a wafer having a first electrical contact pad integrated into a top surface of the wafer, forming a through-hole interconnection extending downward from a first surface of the first electrical contact pad, electrically connecting a die to a second surface of the first electrical contact pad, cutting the wafer to form a channel portion and a connecting portion, disposing an encapsulant over the die and the channel portion, backgrinding the wafer to remove the connecting portion and expose a surface of the through-hole interconnection, disposing a second electrical contact pad over the surface of the through-hole interconnection, disposing a dielectric layer along a side surface of the second electrical contact pad, and singulating the wafer into an individual segment containing the die. The dielectric layer is disposed to form a plurality of lands extending across a bottom surface of the semiconductor device.
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