Flash memory device employing disturbance monitoring scheme
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United States of America Patent
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Jun 30, 2009
Grant Date -
Feb 28, 2008
app pub date -
Mar 30, 2007
filing date -
Aug 28, 2006
priority date (Note) -
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Abstract
A flash memory device comprises a memory cell array including a plurality of NAND strings respectively connected to a plurality of bit lines, and further comprising a disturbed string coupled to a disturbed bit line. In a program operation of the flash memory device, a voltage level of the disturbed bit line is detected to detect program or pass voltage disturbance in the memory cell array.
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