Digital PLL for a system-on-chip for digital control of electronic power devices
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United States of America Patent
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Jul 7, 2009
Grant Date -
Dec 20, 2007
app pub date -
Jun 17, 2007
filing date -
Apr 10, 2002
priority date (Note) -
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Abstract
A digital phase locked loop (DPLL) comprising a digitally implemented voltage controlled oscillator (VCO) for producing a VCO feedback signal, a phase error counter which includes a digital phase-frequency detector for producing a first phase error signal, a quadrature phase detector for producing a second phase error signal and an adder for adding the first and second phase error signals to obtain a combined phase error signal, and two programmable dividers used to cooperatively determine the VCO feedback signal and to provide a DPLL output line sync value synchronized with an input signal.
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