
US Patent No: 7,571,410
Number of patents in Portfolio can not be more than 2000
Resonant tree driven clock distribution grid
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Aug 4, 2009
Issued date -
Apr 26, 2007
filing date -
11/740,479
serial no -
In Force
status
Importance
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Abstract
An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.
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First Claim
Related Publications
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 6,006,025 Method of clock routing for semiconductor chips | 35 | 1997 | |
| 6,205,571 X-Y grid tree tuning method | 29 | 1998 | |
| 6,311,313 X-Y grid tree clock distribution network with tunable tree and grid networks | 88 | 1998 | |
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| 6,556,089 Electronic circuitry | 39 | 2000 | |
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| 2005/0047,445 Clock signal distribution network and method | 5 | 2003 | |
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| 6,690,243 Multi-phase voltage-controlled oscillator at modulated, operating frequency | 21 | 2001 | |
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| 6,057,724 Method and apparatus for synchronized clock distribution | 9 | 1998 | |
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| 5,656,963 Clock distribution network for reducing clock skew | 46 | 1995 | |
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| 5,978,231 Printed wiring board with integrated coil inductor | 64 | 1998 | |
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| 7,091,802 Methods and apparatus based on coplanar striplines | 7 | 2004 | |
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| 6,108,000 Resonant driver apparatus and method | 9 | 1998 | |
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| 2003/0161,128 Multi-layer wiring device, wiring method and wiring characteristic analyzing/predicting method | 7 | 2003 | |
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| 6,753,738 Impedance tuning circuit | 39 | 2002 | |
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| 7,235,477 Multi-layer interconnection circuit module and manufacturing method thereof | 10 | 2005 | |
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| 6,016,082 Low phase noise LC oscillator for microprocessor clock distribution | 23 | 1998 | |
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| 6,972,635 MEMS-based, computer systems, clock generation and oscillator circuits and LC-tank apparatus for use therein | 25 | 2003 | |
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| 7,015,765 Resonant clock distribution for very large scale integrated circuits | 4 | 2004 | |
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| 5,559,478 Highly efficient, complementary, resonant pulse generation | 42 | 1995 | |
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| 5,734,285 Electronic circuit utilizing resonance technique to drive clock inputs of function circuitry for saving power | 30 | 1996 | |
Patent Citation Ranking
Maintenance Fees
| Fee | Large entity fee | small entity fee | micro entity fee | due date |
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| 3.5 Year Payment | $1600.00 | $800.00 | $400.00 | Feb 4, 2013 |
| 7.5 Year Payment | $3600.00 | $1800.00 | $900.00 | Feb 4, 2017 |
| 11.5 Year Payment | $7400.00 | $3700.00 | $1850.00 | Feb 4, 2021 |
| Fee | Large entity fee | small entity fee | micro entity fee |
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