Memory device having a power down exit register
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United States of America Patent
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Aug 11, 2009
Grant Date -
Mar 17, 2005
app pub date -
Sep 17, 2004
filing date -
Mar 10, 1998
priority date (Note) -
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status (Latency Note)
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Abstract
A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.
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